Enable UPL support for RISC-V by dhaval-rivos · Pull Request #6139 · tianocore/edk2

dhaval-rivos · 2024-08-29T12:19:47Z

Description

This patchset enable RISC-V support for UPL.

Fixes a bug in earlier UPL baseline patch related to NULL pointer
Add support for smbios table FDT parser to baseline UPL patch
Enables RISC-V specific build requirements (PCDs etc)
Enable RISC-V entry point (parse FDT argument)
Remove UPL ACPI code with incorrect assumption about table availability
Add support for special purpose memory (HBM)
Add ecam field to support multisegment root bridge
Add root bridge FDT parser and fill up correct data
support for reserved memory parser lib functions
Use Misc fixes for EDK2 #9 functions to create required reserved memory hobs

Breaking change?
- Breaking change - Does this PR cause a break in build or boot behavior?
- Examples: Does it add a new library class or move a module to a different repo.
Impacts security?
- Security - Does this PR have a direct security impact?
- Examples: Crypto algorithm change or buffer overflow fix.
Includes tests?
- Tests - Does this PR include any explicit test code?
- Examples: Unit tests or integration tests.

How This Was Tested

This patchset was tested on an internal Risc-V simulation platform hence:

Requires proper dsc file which stiches correct modules
https://github.com/rivosinc/edk2/tree/dev/dhaval/dev-add-rv-cpuhob is WIP

Integration Instructions

Build instructions:
python UefiPayloadPkg/UniversalPayloadBuild.py -t GCC5 --Fit -a RISCV64 -l "place your addr here" -c */UefiPayloadPkg.dsc

dhaval-rivos · 2024-09-12T15:57:07Z

Thanks then I guess we are all good to go?

…

On Thu, Sep 12, 2024 at 9:25 PM Guo Dong ***@***.***> wrote: ***@***.**** commented on this pull request. ------------------------------ In UefiPayloadPkg/UefiPayloadEntry/AcpiTable.c <#6139 (comment)>: > @@ -128,11 +128,11 @@ ParseAcpiInfo ( // // Verify values for proper operation // - ASSERT (Fadt->Pm1aCntBlk != 0); - ASSERT (Fadt->PmTmrBlk != 0); - ASSERT (Fadt->ResetReg.Address != 0); - ASSERT (Fadt->Pm1aEvtBlk != 0); - ASSERT (Fadt->Gpe0Blk != 0); + // ASSERT (Fadt->Pm1aCntBlk != 0); + // ASSERT (Fadt->PmTmrBlk != 0); + // ASSERT (Fadt->ResetReg.Address != 0); + // ASSERT (Fadt->Pm1aEvtBlk != 0); + // ASSERT (Fadt->Gpe0Blk != 0); ok. once this PR is merged, will create a new PR to update it. — Reply to this email directly, view it on GitHub <#6139 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/A3DE7SA3DCGNKOXYHWRQV3LZWG2NVAVCNFSM6AAAAABNKJVIJ6VHI2DSMVQWIX3LMV43YUDVNRWFEZLROVSXG5CSMV3GSZLXHMZDGMBQG43DQMJQG4> . You are receiving this because you were mentioned.Message ID: ***@***.***>

-- Thanks! =D

gdong1 · 2024-09-12T16:01:58Z

It looks this branch is out-of-date, need rebase it.

Option node provides info that is to be consumed by during metadata creation for other nodes like root bridge; pci-enum-done etc. Handle that dependency by storing option values in a variable and then apply it during post processing. Ideally such cross node dependency should be avoided in design. Scope for futher improvements. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

Not every node has compatible property; avoid parsing nodes which return NULL. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

Expose UPL required PCDs for RISC-V Arch Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

As per specification we are going to accept only one argument at the entry point which is FDT pointer. Grab that and call the entry point. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

We do not need to go deep into verifying all ACPI tables at this stage. TODO: Just a simple ACPI header signature check should be good enough. For now just commenting out asserts that mandate one to have various tables which is not applicable to all platforms. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

We need to let UEFI know that there are cetain memory types which are special purpose (CXL/HBM) etc and we may want to avoid using them for UEFI purposes. Hence UPL needs to know about such memory types. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

In order to properly enable multisegment RB, we need to grab ecam data from the FDT for each bridge. Current UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES struct from MdeModulePkg does not include definition for ecam. In order to maintain backward compatibility and also avoid diverging too much from core, we are going to define a new HOB for UPL segment information and pass it to GetPciSegmentInfo function. Ths function then grabs specifically ecam info from the segment hob along with other rb specific information to create final RB info required by multi segment PCI driver. Additionally we would like to support legacy implementations which rely on ACPIBoard HOB to fill up segment info. So if UplSegmentInfo Hob is not found we try and look for other hob. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>

Devicetree defines a short hand way of defining reserved memory ranges. Add APIs to access such nodes Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

DT has a way to provide reserved images in a simpler tabular manner. UPL should be able to support that. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>

tianocore-assign-reviewers Bot requested review from Benny3345678, ChaselChiu, LiuZhiguang001, Sean-StarLabs, andreiw, gdong1, gguo11837463, jameslu8, lgao4, mdkinney and vlsunil August 29, 2024 12:20