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The context for this is #116344: some target features change the way floats are passed between functions. Changing those target features is unsound as code compiled for the same target may now use different ABIs.

In #134794, I am adding the infrastructure to have the compiler recognize this. But this infrastructure needs to be fed with information about which ABIs exist (e.g. softfloat/hardfloat), and which target features they require or are incompatible with. This will have to be done for each architecture we support.

• x86 (32bit and 64bit):
  • soft-float can be set to swap the ABI; if unset, a hardfloat ABI is used
  • 32bit: uses float registers if !soft-float && x87 (see here). IOW, hardfloat ABI requires x87.
    • except f16 uses SSE registers so that's extra fun, see x86-32 "f16" ABI needs SSE, incompatible with i586 targets #131819
  • 64bit: floats are passed via SSE registers, so likely !soft-float && sse is the relevant check -- IOW, hardfloat ABI requires sse/sse2.
• arm
  • soft-float can be set to swap the ABI; if unset, a hardfloat ABI is used
  • uses float registers if !soft-float && fpregs (see here), so hardfloat ABI requires fpregs
• aarch64
  • doesn't really have a notion of a softfloat ABI, but we offer a softfloat target anyway...
  • uses float registers if fp-armv8 ; Rust makes -neon imply -fp-armv8 so we have to forbid both -- but neon is stable! See The (stable) neon aarch64 target feature is unsound: it changes the float ABI #131058
• riscv
  • "RISC-V has a similar ABI split. -F/-D/-Q is your softfloat/nofloat, but it also comes with the Zfinx/Zdinx/Zqinx variants where floating-point values are carried in the regular registers and the floating-point register file is deleted. Your float-function-features would be +F,-Zfinx, +D,-Zdinx for riscv64gc-unknown-linux (linux does not permit finx). Although I don't think this is as much of a problem because the platform states that +F,+Zfinx is illegal?" (from here)
  • For RISC-V targets, the float ABI can be specified by the llvm_abiname target option. As long as this happens, f/d can be enabled without changing the ABI (LLVM doesn't support q yet). Disabling target features required by the requested ABI will cause LLVM to ignore the ABI. The zfinx/zdinx features don't affect the ABI.
  • Also see Some -Ctarget-features must be restrained on RISCV #132618
• loongarch: see here
• s390x: see here and here
• wasm: add ABI check logic for wasm #157106
• powerpc: powerpc: warn against incorrect values for ABI-relevant target features #157085
• sparc64: Missing target feature ABI checks for Sparc64 #157083
• nvptx: Missing target feature ABI checks for nvptx #157532

Tier 3 only:

• bpf
• csky
• hexagon
• mips
• m68k
• sparc32
• more?